You are here: Home Page » /aps » /aps/infrastructure » Carrying the bits

Carrying the bits

May 1, 2005 12:00 PM, By Michael Robin

Figure 1. Simplified block diagram of Rec. 601 4:2:2 encoder with time division multiplexed 27MW/s bit-parallel output. Click here to see an enlarged diagram.

Figure 1 shows the simplified block diagram of a Rec. 601 4:2:2 encoder. Each of the three component video channels (E'_Y, E'_B-Y and E'_R-Y) consists of a low-pass (anti-aliasing) filter and the associated A/D. A clock generator controls the sampling process. The output of each converter features a conductor (pair of wires) for each of the bits plus an additional conductor carrying the clock. The clock is required to synchronize the various serializer functions as well as the D/A converters in the decoders.

Information is carried word-by-word, meaning that the bits are carried in parallel. This requires a large number of conductors of equal length to ensure that the bits arrive in time at the destination. This requirement is relatively easy to meet inside a studio, but it creates a nightmare in a large teleproduction center. While it is feasible to carry the bits in parallel in a studio environment, it is impossible to carry them on a telco distribution system.

Figure 2. NRZ- and NRZI-channel coding characteristics. Click here to see an enlarged diagram.

Therefore, since the beginning of digital technology, various scenarios were developed aimed at using a single conductor to carry the bits in sequence (bit-serial). All of them have something in common: They use the concept of self-clocking, which means that the bit-serial signal has to carry information allowing the receiver to regenerate the missing clock signal.

The channel coding

The channel coding describes the manner in which the “ones” and “zeros” of the data stream are represented on the transmission path. There are many channel coding standards. They all aim at optimizing some aspect of the bit-serial digital signal such as the spectral distribution, the DC content and the clock recovery.

The simplest and most commonly used channel code is NRZ. NRZ is characterized by logic “one” having a well-defined DC level, and logic “zero” having a well-defined lower DC level. The bit-serial digital signal is self-clocking.

The receiver contains a clock regenerator. The regenerator recreates the clock through a phase-locked-loop (PLL) controlled oscillator (VCO). The PLL derives its reference from the zero-to-one-to-zero digital signal transitions. The NRZ code may result in long strings of ones and zeros. These long “monotonous” data strings have no transitions, resulting in long periods of time during which the PLL reference is not refreshed.

Figure 3. Simplified block diagram of a Rec. 601 4:2:2 serializer. Click here to see an enlarged diagram.

The accurate sampling of the bit-serial digital signal in the receiver during these periods depends on the stability of the clock VCO. In addition, the NRZ code has a zero frequency (DC) component, which varies with the nature of the data stream, as well as a significant low-frequency content making it inappropriate for AC-coupled receivers. For these reasons, the NRZ code is not used in its basic form in bit-serial digital video transmissions.

Bit-serial digital video transmissions use a derivative of the NRZ code, the Non Return to Zero Inverted (NRZI) code. Figure 2 shows an example of an NRZ-coded digital signal and the derived NRZI-coded signal.

NRZI codes logic zeros as a DC level (zero or one) and logic ones as a transition. When the NRZ-coded digital signal is a long string of ones, the derived NRZI-coded signal is a square wave at one-half the clock frequency. As shown, for a given binary sequence, an NRZI-coded signal has more transitions per unit of time than an NRZ-coded signal, resulting in improved clock regenerator PLL operation.

Figure 4. Block diagram of a scrambler. Click here to see an enlarged diagram.

Provided that the system limits the maximum number of zeros in the data stream, the receiver clock regeneration works quite well. The standards meet this requirement by reserving the all-zero word for sync purposes only. The NRZI, while superior to the NRZ coding, still has a DC component and a significant low-frequency content.

Bit-serial digital video transmissions use a derivative of A further improvement in the receiver clock recovery is obtained through scrambling. The scrambler randomizes long sequences of zeros and ones as well as repetitive data patterns, which could result in clock regeneration difficulties. It helps eliminate the DC content and provides sufficient signal transitions for reliable clock recovery.

Figure 3 shows the block diagram of a Rec. 601 4:2:2 serializer consisting of a scrambler, followed by an NRZ-to-NRZI encoder. The scrambler produces a Pseudorandom Binary Sequence (PRBS), which, in turn, is combined with transmitted data in order to randomize it. It consists of a nine-stage shift register (nine sections of clocked Master Slave D-Flip-Flop marked D in the diagram) with associated feedback. The feedback signals are combined by “Exclusive OR” adders (marked in the diagram) with the following input versus output truth table:

The scrambling concept

0 ( at input A ) + 0 ( at input B ) = 0 ( at output )

0 ( at input A ) + 1 ( at input B ) = 1 ( at output )

1 ( at input A ) + 0 ( at input B ) = 1 ( at output )

1 ( at input A ) + 1 ( at input B ) = 0 ( at output )

Figure 5. Simplified block diagram of a Rec. 601 4:2:2 deserializer. Click here to see an enlarged diagram.

The scrambling function is classified using a shorthand method of describing the feedback connection known as the “Characteristic Polynomial”. For the nine-stage register illustrated in Figure 4, the polynomial is: G1(X) = X⁹ + X⁴ + 1. The scrambler can produce long runs of ones. These are converted to transitions by an NRZ-to-NRZI converter consisting of a single stage shift register with an XOR gate. The polynomial of the NRZI converter is: G2(X) = X + 1.

Figure 3 shows a simplified block diagram of a Rec. 601 4:2:2 serializer using the scrambled NRZI. The resulting signal is often called Pseudo Noise because it has a noise-like spectrum and, as a result, the required bandwidth remains unchanged. By comparison, the AES/EBU digital audio signal distribution uses a different channel coding called the BPM (Bi-phase Mark), which doubles the bit-rate and, therefore, the required bandwidth. While this is acceptable with the relatively low bitrate of digital audio (3.072Mb/s), it is unacceptable with the high bit-rates of SDTV (270Mb/s) and HDTV (1.485Gb/s).

Figure 6. Block diagram of a descrambler. Click here to see an enlarged diagram.

Figure 5 shows a simplified block diagram of a Rec. 601 4:2:2 deserializer. Cable losses are compensated by a self-adjusting equalizer. The original data is recovered by an NRZI-to-NRZ converter, followed by a descrambler.

Figure 6 shows the block diagram of the descrambler. The logic arrangement is identical to the one used in the scrambler, except that “feedforward” is used instead of the feedback. The same random sequence, which is added to the signal before transmission, is subtracted at the decoder, resulting in the recovered data being identical to the original data.

Michael Robin, a fellow of the SMPTE and former engineer with the Canadian Broadcasting Corp.'s engineering headquarters, is an independent broadcast consultant located in Montreal, Canada. He is co-author of “Digital Television Fundamentals,” published by McGraw-Hill and translated into Chinese and Japanese.

Send questions and comments to: michael_robin@primediabusiness.com